vasu
Minnow
Posts: 1
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Post by vasu on Sept 27, 2023 17:19:43 GMT
Could we please add RISC-V architecture enumerations to the ProcessorArchitecture and InstructionSet properties?
Specifically:
"ProcessorArchitecture": { "enum": [ "x86", "IA-64", "ARM", "MIPS", "Power", <b> "RISC-V",</b> "OEM" ], "enumDescriptions": { "ARM": "ARM.", "IA-64": "Intel Itanium.", "MIPS": "MIPS.", "OEM": "OEM-defined.", "Power": "Power.", <b> "RISC-V": "RV32 or RV64",</b> "x86": "x86 or x86-64." }, ... }
"InstructionSet": { "enum": [ "x86", "x86-64", "IA-64", "ARM-A32", "ARM-A64", "MIPS32", "MIPS64", "PowerISA", <b> "RV32", "RV64", </b> "OEM" ], "enumDescriptions": { "ARM-A32": "ARM 32-bit.", "ARM-A64": "ARM 64-bit.", "IA-64": "Intel IA-64.", "MIPS32": "MIPS 32-bit.", "MIPS64": "MIPS 64-bit.", "OEM": "OEM-defined.", "PowerISA": "PowerISA-64 or PowerISA-32.", <b> "RV32": "RISC-V 32-bit", "RV64": "RISC-V 64-bit", </b> "x86": "x86 32-bit.", "x86-64": "x86 64-bit." }, ... },
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